Category: InGaAs Etch
Scientific Paper on InGaAs MOSFETs Using InGaAs Plasma Etching from MIT
A CMOS-Compatible Fabrication Process for Scaled Self-Aligned InGaAs MOSFETs
Lin, J., D. A. Antoniadis, and J. A. del Alamo
presented at Compound Semiconductor Manufacturing Technology Conference (CS MANTECH), Scottsdale, AZ, May 18-21, 2015, pp. 239-242.
Samco ICP etching system, RIE-200iP was used for optimization of InGaAs/InAlAs/InP dry etching process.
Scientific Paper on InGaAs Nanowire Fabrication Using InGaAs Plasma Etching from MIT
Nanometer-Scale Vertical-Sidewall Reactive Ion Etching of InGaAs for 3-D III-V MOSFETs
Xin Zhao and Jesús A. del Alamo
Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139 USA
IEEE ELECTRON DEVICE LETTERS (2014) 35, 5
Samco ICP etch system was used for fabrication of InGaAs nanowires. The nanowires showed vertical and smooth sidewalls by optimization of the etch recipe.
Massachusetts Institute of Technology (MIT) is one of the proprietary customers of Samco plasma etching systems. They use our process equipment for plasma etching of III-V materials such as GaN, GaAs and InGaAs in various device projects.
For our process capabilities of GaAs plasma etching, please visit the page below.
GaAs Dry Etching Process (ICP-RIE)