Process Solutions for TSV-Based 3D IC Integration
SAMCO Inc. > Markets > Process Solutions for TSV-Based 3D IC Integration
1. Via Hole Fabrication using the Bosch Process
![Via Hole Fabrication using the Bosch Process](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/TSV-Process-01-01.gif?fit=350%2C382&ssl=1)
![silicon etching for TSV processing](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/01/silicon-etching-for-TSV-2.jpg?fit=350%2C350&ssl=1)
![Process Repeatability of Silicon Via Hole Etching](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/Process-Repeatability-of-Si-Via-Hole-Etching.jpg?fit=350%2C350&ssl=1)
Precise tilt control is critical in the silicon via hole fabrication because tilt angle of just 1° could result in the misalignment of a 200 μm thick TSV by as much as 2 μm. An absolutely vertical via hole etching can be achieved with uniform plasma discharge. Tilt angle and etch depth are highly stable in consecutive run of 25 wafers. Furthermore, sidewall smoothing process will reduce scallop size on sidewalls and prevent delamination of Cu plug.
![Arrow](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/Arrow.jpg?fit=50%2C92&ssl=1)
2. Photoresist Ashing
![Photoresist Ahing for TSV Fabrication](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/TSV-Process-02.gif?fit=350%2C382&ssl=1)
![User-friendly interface for production](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/RIE-System-for-production.jpg?fit=350%2C350&ssl=1)
![Double cassette and single arm robot for wafer transfer](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2015/12/RIE-200C-Robot.jpg?fit=350%2C350&ssl=1)
Samco RIE systems with double atmospheric cassettes minimize downtime for wafer transfer and improve throughput of photoresist plasma ashing process.
![Arrow](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/Arrow.jpg?fit=50%2C92&ssl=1)
3. Insulation Film Deposition on Via Hole
![Insulation Film Deposition on Via Hole](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/TSV-Process-03.gif?fit=350%2C382&ssl=1)
![Excellent Step Coverage of Cathode PECVD using TEOS](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2015/11/Cahode-PECVD-Step-Coverage1.jpg?fit=350%2C350&ssl=1)
![Excellent Step Coverage of Cathode PECVD using TEOS](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2015/11/Cahode-PECVD-Step-Coverage2.jpg?fit=350%2C350&ssl=1)
A TEOS-Oxide film with excellent step coverage was deposited using Samco’s unique Cathode PECVD technology.
![Leakage Current of TSV SiO2 Passivation](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/08/Leakage-Current-of-TSV-SiO2-Passivation.jpg?fit=350%2C350&ssl=1)
Another process feature of our plasma CVD technologies is low-temperature deposition. There are high demands in advanced packaging research communities for low-temperature processes due to the use of temperature-sensitive adhesives which are used for temporary wafer bonding of thinned wafers. Samco offers low-temperature PECVD process solutions (including under 80°C) of SiO2 and SiNx deposition to meet such demands. SiO2 deposited at 120°C or 150°C showed low leakage (~ nA) between silicon substrate and passivation with 100 μm deep via.
![Arrow](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/Arrow.jpg?fit=50%2C92&ssl=1)
4. Exposure of Lower Electrode by SiO2 Etching
![Exposure of Lower Electrode by SiO2 Etching](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/TSV-Process-04.gif?fit=350%2C382&ssl=1)
![Oxide Etching on Via Hole Bottom (Before Process)](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/Oxide-Etching-on-Via-Hole-Bottom-Before-Process.jpg?fit=350%2C350&ssl=1)
![Oxide Etching on Via Hole Bottom (After Process)](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/Oxide-Etching-on-Via-Hole-Bottom-After-Process.jpg?fit=350%2C350&ssl=1)
A SiO2 film on via hole bottom was successfully removed by RIE process.
![Arrow](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/Arrow.jpg?fit=50%2C92&ssl=1)
5. Barrier Layer Formation
![Barrier Layer Formation](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/TSV-Process-6.jpg?fit=350%2C350&ssl=1)
6. Cu Electroplating
![Cu Electroplating](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/TSV-Process-7.jpg?fit=350%2C350&ssl=1)
7. CMP
![Chemical Mechanical Polishing (CMP)](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/TSV-Process-8.jpg?fit=350%2C350&ssl=1)
![Arrow](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/Arrow.jpg?fit=50%2C92&ssl=1)
8. Cu Plug Exposure by Dry Etching
![Cu Plug Exposure by Dry Etching](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/TSV-Process-08.gif?fit=350%2C382&ssl=1)
![RIE System Design](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/RIE-System-Design.jpg?fit=350%2C350&ssl=1)
![RIE-10NR](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/RIE-System-Chamber.jpg?fit=350%2C350&ssl=1)
Symmetrical evacuation and optimized gas manifold design of RIE systems enable high-uniformity etching over the sample stage.
![Arrow](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/Arrow.jpg?fit=50%2C92&ssl=1)
9. SiO2 Passivation Film Deposition by PECVD
![Passivation Film Deposition by PECVD](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/TSV-Process-09.gif?fit=350%2C382&ssl=1)
![SiO2 Film Stress Control by Cathode PECVD](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/SiO2-Film-Stress-Control-by-Cathode-PECVD.jpg?fit=350%2C350&ssl=1)
Film stress of SiO2 passivation is highly controllable using Cathode PECVD technology. By adjusting process time of compressive layers and tensile layers, the film stress is stable even 24 hours after the deposition.
![Arrow](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/Arrow.jpg?fit=50%2C92&ssl=1)
10. Cu Plug Exposure by SiO2 Plasma Etching
![Cu Plug Exposure by SiO2 Etching](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/TSV-Process-10.gif?fit=350%2C382&ssl=1)
![N2 purge cassette chamber](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/N2-purge-cassette-chamber.jpg?fit=350%2C350&ssl=1)
![Robot Arm Wafer Handling](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/Robot-arm-wafer-handling-2.jpg?fit=350%2C350&ssl=1)
Double Cassettes and multi-joint robot wafer handling of Samco’s atmospheric cassette RIE systems improve throughput of SiO2 etching.
![Arrow](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/Arrow.jpg?fit=50%2C92&ssl=1)
11. Photoresist Plasma Ashing
![Photoresist Removal](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/03/TSV-Process-11.gif?fit=350%2C382&ssl=1)
![cassette loading uv ozone cleaner](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/Atmospheric-Cassette-UV-Ozone-Cleaners-2.jpg?fit=350%2C350&ssl=1)
![Loadlock RIE Systems](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/Loadlock-RIE-Systems.jpg?fit=350%2C350&ssl=1)
Samco offers multiple systems and technologies to meet customers’ demands for photoresist plasma ashing process.
![Arrow](https://i0.wp.com/www.samcointl.com/opto/wp-content/uploads/2016/02/Arrow.jpg?fit=50%2C92&ssl=1)