Process Solutions for TSV-Based 3D IC Integration

SAMCO Inc. > Markets > Process Solutions for TSV-Based 3D IC Integration

 1. Via Hole Fabrication using the Bosch Process

Via Hole Fabrication using the Bosch Process
silicon etching for TSV processing
Process Repeatability of Silicon Via Hole Etching

Precise tilt control is critical in the silicon via hole fabrication because tilt angle of just 1° could result in the misalignment of a 200 μm thick TSV by as much as 2 μm. An absolutely vertical via hole etching can be achieved with uniform plasma discharge. Tilt angle and etch depth are highly stable in consecutive run of 25 wafers. Furthermore, sidewall smoothing process will reduce scallop size on sidewalls and prevent delamination of Cu plug.

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2. Photoresist Ashing

Photoresist Ahing for TSV Fabrication
User-friendly interface for production
Double cassette and single arm robot for wafer transfer

SAMCO RIE systems with double atmospheric cassettes minimize downtime for wafer transfer and improve throughput of photoresist ashing process.

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3. Insulation Film Deposition on Via Hole

Insulation Film Deposition on Via Hole
Excellent Step Coverage of Cathode PECVD using TEOS
Excellent Step Coverage of Cathode PECVD using TEOS

A TEOS-Oxide film with excellent step coverage was deposited using SAMCO’s unique Cathode PECVD technology.

Leakage Current of TSV SiO2 Passivation

Another process feature of our plasma CVD technologies is low-temperature deposition. There are high demands in advanced packaging research communities for low-temperature processes due to the use of temperature-sensitive adhesives which are used for temporary wafer bonding of thinned wafers. Samco offers low-temperature PECVD process solutions (including under 80°C) of SiO2 and SiNx deposition to meet such demands. SiO2 deposited at 120°C or 150°C showed low leakage (~ nA) between silicon substrate and passivation with 100 μm deep via.

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4. Exposure of Lower Electrode by SiO2 Etching

Exposure of Lower Electrode by SiO2 Etching
Oxide Etching on Via Hole Bottom (Before Process)
Oxide Etching on Via Hole Bottom (After Process)

A SiO2 film on via hole bottom was successfully removed by RIE process.

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5. Barrier Layer Formation

Barrier Layer Formation

6. Cu Electroplating

Cu Electroplating

7. CMP

Chemical Mechanical Polishing (CMP)
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8. Cu Plug Exposure by Dry Etching

Cu Plug Exposure by Dry Etching
RIE System Design
RIE plasma etcher

Symmetrical evacuation and optimized gas manifold design of RIE systems enable high-uniformity etching over the sample stage.

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9. SiO2 Passivation Film Deposition by PECVD

Passivation Film Deposition by PECVD
SiO2 Film Stress Control by Cathode PECVD

Film stress of SiO2 passivation is highly controllable using Cathode PECVD technology. By adjusting process time of compressive layers and tensile layers, the film stress is stable even 24 hours after the deposition.

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10. Cu Plug Exposure by SiO2 Plasma Etching

Cu Plug Exposure by SiO2 Etching
N2 purge cassette chamber
Robot Arm Wafer Handling

Double Cassettes and multi-joint robot wafer handling of SAMCO’s atmospheric cassette RIE systems improve throughput of SiO2 etching.

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11. Photoresist Removal

Photoresist Removal
cassette loading uv ozone cleaner
Loadlock RIE Systems

SAMCO offers multiple systems and technologies to meet customers’ demands for photoresist removal process.

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TSV
TSV (Via-First)
TSV (Via First)

Photo courtesy of WALTS CO., LTD

Contact SAMCO for more product information
Any questions? Contact us for more detail.
Contact SAMCO for more product information
Any questions? Contact us for more detail.
Contact SAMCO for more product information
Any questions? Contact us for more detail.
Contact SAMCO for more product information
Contact us for more detail.
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