1. Via Hole Fabrication using the Bosch Process
Precise tilt control is critical in the silicon via hole fabrication because tilt angle of just 1° could result in the misalignment of a 200 μm thick TSV by as much as 2 μm. An absolutely vertical via hole etching can be achieved with uniform plasma discharge. Tilt angle and etch depth are highly stable in consecutive run of 25 wafers. Furthermore, sidewall smoothing process will reduce scallop size on sidewalls and prevent delamination of Cu plug.
3. Insulation Film Deposition on Via Hole
A TEOS-Oxide film with excellent step coverage was deposited using SAMCO’s unique Cathode PECVD technology.
Another process feature of our plasma CVD technologies is low-temperature deposition. There are high demands in advanced packaging research communities for low-temperature processes due to the use of temperature-sensitive adhesives which are used for temporary wafer bonding of thinned wafers. Samco offers low-temperature PECVD process solutions (including under 80°C) of SiO2 and SiNx deposition to meet such demands. SiO2 deposited at 120°C or 150°C showed low leakage (~ nA) between silicon substrate and passivation with 100 μm deep via.
5. Barrier Layer Formation
6. Cu Electroplating
9. SiO2 Passivation Film Deposition by PECVD
Film stress of SiO2 passivation is highly controllable using Cathode PECVD technology. By adjusting process time of compressive layers and tensile layers, the film stress is stable even 24 hours after the deposition.